The main objective of this course is to obtain a basic level of Digital Electronics knowledge and set the stage to perform the analysis and design of complex digital electronic circuits. This training is subjects completed in subsequent courses such as: Circuits Electronics, Digital Systems I and II, Electronic Systems Engineering, Processor Architecture and Design of Digital Electronic Systems.
The most significant evolution of digital electronics in recent years has been on the degree of complexity of the systems that are carried with it, from simple components to complete systems performing. For address the problem of high complexity has chosen to make a approach that defines new levels of abstraction on the classic logic, such as RTL and functional.
In the approach of the program is part of the course with an introduction of electrical and logical levels to focus then the greater weight of thesubject to structural and functional levels, for introducing the VHDL hardware description language.
The main objective of this course is to obtain a basic level of Digital Electronics knowledge and set the stage to perform the analysis and design of complex digital electronic circuits. This training is subjects completed in subsequent courses such as: Circuits Electronics, Digital Systems I and II, Electronic Systems Engineering,
Processor Architecture and Design of Digital Electronic Systems.
The most significant evolution of digital electronics in recent years has been on the degree of complexity of the systems that are carried with it, from simple components to complete systems performing. For address the problem of high complexity has chosen to make a approach that defines new levels of abstraction on the classic logic, such as RTL and functional.
In the approach of the program is part of the course with an introduction of electrical and logical levels to focus then the greater weight of the subject to structural and functional levels, for introducing the VHDL hardware description language.
Learning Objectives
Powers assigned to the subject and level of
ACQUISITION
Code
Competition
Level
CG1-
CG13
All subjects contribute Curriculum
greater or lesser extent to the achievement of the
general skills of the graduate profile.
1
CECT9
Capacity for analysis and design of combinational circuits
and sequential, synchronous and asynchronous, and use of
microprocessors and integrated circuits.
3
CECT10
Knowledge and application of the fundamentals of languages
description of hardware devices
2
LEGEND:
Acquisition Level 1: Basic
Acquisition level 2: Middle
Acquisition Level 3: Advanced
SPECIFIC CONTENT
Block / Topic / Chapter
Paragraph
Indicators
Related
Topic 1: Coding
Information
1.1 Introduction Digital Electronics
I1
1.2 Abstraction digital (vs. analog. Digital)
I1
1.3 Numbering Systems
I1
1.4 Representation negative numbers
I1
1.5 Boolean algebra. Axioms
I2, I3
1.6 Basic Operators. Truth Table
I2, I3
1.7 Logic gates simple and complex
I2, I3
1.8 Karnaugh Maps
I2, I3
2.1 Introduction to programmable logic devices
to hardware description languages (VHDL)
I7
Item 2: Devices
2.2 Structure VHDL code
I7
Programmable Logic (VHDL)
2.3 Basic Syntax
I7
Item 3: Circuits
Combinational
3.1 Multiplexers.
I4, I7
3.2 Interconnection of several MUXes.
I4
3.3 Implementation of functions with MUXes.
I4
3.4 Encoders and Decoders
I4, I7
3.5 Interconnection of multiple coders
I4
3.6 Comparators
I4, I7
3.7 Adder
I4, I7
Nvm 08.03
I4
Item 4: Circuits
Sequential
4.1 Basic bistable element
I5
4.2 Set-Reset Scale.
I5
4.3 Bistable level assets (latch)
I5
4.4 Latch CLK edge assets (flip-flops): type-D,
JK and T-type
I5
4.5 Timing.
I5
4.6 Records Storage.
I5, I7
4.7 Counters
I5, I7
4.8 Shift registers
I5, I7
Item 5: Automata
5.1 Moore and Mealy machines.
I6
5.2 State Diagram.
I6, I7
5.3 Table of automata transitions.
I6
Qualification Criteria
Students will be assessed by continuous assessment default. In
compliance with the Regulations Assessment of the Technical University of Madrid,
Students who wish to be evaluated by a single long final test
when you inform the Director of the Department of Electronic Engineering
on application to the registry of the School of
Telecommunications Engineers before the day November 20, 2012. The
presentation of this paper constitute a waiver automatic continuous assessment.
The final mark will be obtained through continuous assessment sum of the
ratings for the following evaluation activities:
• Resolution and delivery of classroom exercises: mean 10% of the grade
end.
• 4-control tests conducted during class time representing
A total of 10% of the final grade.
• 2 partial evaluation tests: the first of which represents 30% of the
final grade and the second by 50%
Links:
[1] https://www.die.upm.es/en/taxonomy/term/27
[2] https://www.die.upm.es/sites/default/files/EDIG.pdf
[3] https://www.die.upm.es/en/perfil/miguel-angel-s%C3%A1nchez-garc%C3%AD-0
[4] https://www.die.upm.es/en/perfil/alvaro-araujo-pinto
[5] https://www.die.upm.es/en/perfil/luis-fernando-d%C2%B4haro-enr%C3%ADquez-0
[6] https://www.die.upm.es/en/content/octavio-nieto-taladriz-garc%C3%AD
[7] https://www.die.upm.es/en/perfil/jose-manuel-pardo-mu%C3%B1oz
