From idea to silicon: the tape-out of an ASIC in industrial practice, by Iñaki Ormaetxea

Summary

The development of a modern ASIC on advanced technology nodes is a complex process that goes far beyond RTL design or verification of individual blocks. From the initial product definition to the arrival of the silicon in the lab, tape-out involves a succession of highly interdependent stages in which technical decisions, estimations and architectural compromises condition the entire project.

This talk will describe, at a high level, the design process of a digital integrated circuit from the practical perspective of an IP design and verification engineer in a leading semiconductor company. The different phases of the ASIC life cycle will be covered, such as: specification definition, architecture and microarchitecture proposals, area and power estimation, IP implementation and verification, subsystem and top level integration, interaction with Physical Design, emulation, test preparation and laboratory validation after silicon acceptance.

The technical and organizational intricacies that characterize tape-outs in advanced technologies will be addressed, as well as the difficulties inherent in large-scale, highly complex projects. From a real-world perspective, it will highlight how each stage impacts the day-to-day work of the designer and tester, and how early decisions can be amplified throughout the project.

The goal is to provide an honest view of how an idea is taken from conception to functional silicon, showing both the technical dimension and the practical reality of large ASIC projects in today’s industry.

Lecture given by Iñaki Ormaetxea, silicon design engineer at AMD and member of its technical management team.

Speaker

Iñaki Ormaetxea Orobengoa is an engineer in industrial and automatic electronics from the University of the Basque Country (2018), completed an international academic year at San Diego State University (USA, 2016-2017) and completed a Master in Electronic Systems at the Polytechnic University of Madrid (ETSIT-UPM) (2019). During his formative years he collaborated with the VLSI Design and Test Laboratory (SDSU) and the Integrated Systems Laboratory (LSI-UPM), and completed several internships at the Ikerlan technology center (Mondragon, Gipuzkoa), before starting his professional career in Scotland at Xilinx / Advanced Micro Devices (AMD).

He has 7 years of experience in the semiconductor industry at Xilinx/AMD, where he has evolved from machine learning oriented FPGA engineer to be part of the direct technical team as ASIC design engineer. He has worked on the development of integrated circuits for interconnects (DPU/AI-NICs) for GPUs and servers, being responsible for IP blocks in advanced technologies, having participated in several ASIC tape-outs at 7nm and 3nm node. His responsibilities have included micro-architecture definition, RTL design, verification (UVM), performance profiling and platform bring-up.

In parallel, he co-founded the technology startup Autnet (2019-2023), focused on the digitization of the construction sector.

Organize

UPM-Indra Chip Chair