Skip to content
Integrated Systems Laboratory (LSI)

NEUROSPACEWARE (PID2022-141391OB)

Tecnologias y plataformas emergentes para computación neuromórfica en espacio (NeuroSpaceWare)

Summary

Neuromorphic hardware, which implements the third generation of neural networks, the spiking neural networks, is poised to revolutionize the field of brain-inspired computing due to its low power consumption and high fault tolerance. These two characteristics hold great promise for the space sector. However, the current development of the technique is still far from its potential and there is still much room for improvement both in energy efficiency and at the algorithmic level. One of the most promising solutions is the use of emerging technologies due to their characteristics: multi-level resistance, grouping in crossbars, merging of memory functionalities and arithmetic computation. However, these technologies are still immature and there are several open challenges that need to be addressed. Another path to the expected potential lies in the exploration of new digital architectures that take advantage of the extreme parallelism of neuromorphic computing. In this respect, FPGAs also appear to be very promising platforms.

NEUROSPACEWARE focuses on the generation of knowledge for novel neuromorphic hardware solutions, from device to architectural level, subject to the stringent constraints of space applications. Further specifying, the project aims at establishing new paradigms and circuit topologies employing both ETs and FPGAs (field programmable gate arrays) in the areas of neural and synaptic models, network topologies, and neural information encoding, taking into account the dependability and power budget restrictions imposed by space missions.

Researchers

UPM Team

  • María Luisa López-Vallejo (Investigador principal)
  • Pablo Ituero Herrero (Investigador principal)
  • Amadeo de Gracia Herranz
  • Samuel López Asunción
  • Javier de Mena Pacheco
  • Miguel Villacañas Rebollo
  • Cristina Bermúdez Martín

UPC Team

  • Rosa Rodríguez Montañés (Investigador principal)
  • Antonio Rubio Solá (Investigador principal)
  • Salvador Manich Bou
  • Álvaro Gómez Pau
  • Elia Mateu Barriendos
  • Daniel Arumí Delgado
  • Ioanis Chatzipaschalis
  • Antonio Calomarde Palomino
  • Vahab Mabhoubi
  • Josep Rius Vázquez
  • Victor Manuel Suñe Socias

Publications

PhD Thesis
  1. Samuel López Asunción, FPGA-Based Acceleration for Emerging Neuromorphic Computing Paradigms. Sobresaliente cum laude. UPM. 24 de junio de 2024.
  2. Javier de Mena Pacheco, dirigida por M. López Vallejo. Design of Ultra-Low Power and Area Circuits for Cell-Size Microsystems. UPM. 31 de enero de 2025.
Journal papers
  1. López-Asunción, S. and Ituero, P. Enabling Efficient On-Edge Spiking Neural Network Acceleration with Highly Flexible FPGA Architectures. Electronics. 2024.
  2. Pistolesi, L., Ravelli, L., Glukhov, A., de Gracia Herranz, A., Lopez-Vallejo, M., Carissimi, M., … & Ielmini, D. (2024). Differential Phase Change Memory (PCM) Cell for Drift-Compensated In-Memory Computing. IEEE Transactions on Electron Devices. 2024.
  3. de Mena Pacheco, J., Carrillo, J. M., Palacios, T., & Lopez-Vallejo, M. (2024). A Highly Power-and Area-Efficient PMU for Cell-Size Autonomous Microsystems. IEEE Transactions on Circuits and Systems I: Regular Papers.
  4. Pacheco, J. D. M., Palacios, T., Hempel, M., & Vallejo, M. L. (2024). A Highly Linear Ultra-Low-Area-and-Power CMOS Voltage-Controlled Oscillator for Autonomous Microsystems. Micromachines, 15(10), 1193.
  5. López-Asunción, S., González-López, J., García-de-la-Cueva, C., Lopez-Vallejo, M., & Grajal, J. (2024). Design and Implementation of a Real-Time Low-Latency Automatic Modulation Classifier. IEEE Transactions on Instrumentation and Measurement.
  6. de Cabiedes, B. G., de Mena Pacheco, J., de Gracia Herranz, A., & Lopez-Vallejo, M. (2025). An ultra-low-power flip-flop with near-threshold robust operation and redundant-free internal clock transitions. IEEE Transactions on Circuits and Systems I: Regular Papers.
Conference papers
  1. Efficient on-chip cross-subject local field potential decoding for implantable neural interfaces. 2025 International Joint Conference on Neural Networks. Comunicación oral. Arnau Marin-Llobet, Victoria Clerico, Samuel Lopez-Asuncion, Arnau Manasanch, Irene Merino, Melody Torao-Angosto, Pablo Ituero, Maria V. Sanchez-Vives, Leonardo Dalla Porta.
  2. Cristina Bermúdez, Samuel López-Asunción, Pablo Ituero. Design Space Exploration of FPGA-Based Spiking Neural Networks for Angle of Arrival Detection. 2025. XL Conference on Design of Circuits and Integrated Systems (DCIS 2025). Comunicación oral.
  3. de Gracia Herranz, A., Gutierrez de Cabiedes, B., de Mena Pacheco, J. and Lopez-Vallejo, M. Ultra-Narrow Current Pulses Measurement Using a Cost-Effective Instrumentation System. XL Conference on Design of Circuits and Integrated Systems (DCIS 2025).
  4. Oliver Schrape, Anselm Breitenreiter, Li Lu, Marko Andjelkovic, Ernesto Pun-García, Marisa Lopez-Vallejo and Milos Krstic. Low Overhead Self-Correction in Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flops for Space Applications. 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct. 2025, Barcelona, Spain.
  5. Iturbe, X., Camuñas-Mesa, L., Linares-Barranco, B., Serrano-Gotarredona, T., … Ituero, P., López-Vallejo, M., Rodríguez, R., Rubio, A., … & Gabarrón, A. (2024, July). Neuromorphic Technology Insights in Spain. In 2024 IEEE 24th International Conference on Nanotechnology (NANO) (pp. 1-11). IEEE.
  6. Pacheco, J. D. M., De Cabiedes, B. G., Herranz, A. D. G., & Lopez-Vallejo, M. (2024, November). A Lightweight Analog RFID Front-End for Interfacing Sensors. In 2024 39th Conference on Design of Circuits and Integrated Systems (DCIS) (pp. 1-6). IEEE.
  7. Schrape, O., Breitenreiter, A., Lu, L., Andjelković, M., Pun-Garcia, E., López-Vallejo, M., & Krstić, M. (2024, October). Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction. In 2024 IEEE Nordic Circuits and Systems Conference (NorCAS) (pp. 1-4). IEEE.
  8. de Gracia Herranz, A., & López-Vallejo, M. (2024, July). Applying the Time-Domain Paradigm to Interface Multilevel Phase Change Memory. In 2024 IEEE 24th International Conference on Nanotechnology (NANO) (pp. 405-408). IEEE.
  9. Pistolesi, L., Glukhov, A., de Gracia Herranz, A., Lopez-Vallejo, M., Carissimi, M., Pasotti, M., … & Ielmini, D. (2024, April). Drift compensation in multilevel PCM for in-memory computing accelerators. In 2024 IEEE International Reliability Physics Symposium (IRPS) (pp. 1-4). IEEE.
  10. de Gracia Herranz, A., López-Vallejo, M. (2024, July). Design Challenges on Interfacing Multilevel Memristive Cells. 1st Workshop on Memristors, Barcelona.
  11. de Gracia Herranz, A., Villacañas M. and López-Vallejo, M. (2024, July). The Commutative Problem in Vector Matrix Multiplication based on Memristive Crossbar Architectures. Second Workshop on Memristors, Barcelona (June 2025).