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Asignaturas de grado
Electronic Circuits (CELT)
DESCRIPTION OF THE COURSE
The aim of this course is to develop a practice of a system
complex analog-digital electronic starting with a description and a
basic specifications.
The course begins with a theoretical classes where students receive information
on decomposition in said system modules, the methods
convenient for design and recommendations for installation on the plate
insertion. Furthermore, in the above indicated classes are more procedures
suitable for detecting performance problems and their solution to
Throughout the development of the circuit.
During the course of the course, students will use the means available
laboratory B-043 for the development of the practice, with the
help of teachers. Some classes are regularly taught theoretical
short duration in the laboratory.
Finally, the student will have to write a memory circuit technique
performed.
SPECIFIC CONTENT
Block / Theme /
Chapter
Paragraph
Indicators
Related
two
Block 1:
Description
system
electronic
design
1.1 Description of the electronic system to be
developed throughout the course.
I1
1.2 Analysis of decomposition into modules.
I2
1.3 Details of each module.
I2
1.4 Interactions between.
I2
1.5 Basic specifications must meet the system
I1
Block 2:
Development
analog part
2.1 Distribution of food:
2.1.1 star topology power
2.1.2 Decoupling Capacitors
2.1.3 LEDs alert shorts
2.1.4 Efficient insertion of plates
I3
2.2 Rules General Assembly:
2.1.1 Power Operational Amplifiers
2.1.2 Transportation of signals through the circuit
2.1.3 Noise reduction: parasitic capacitances and
radiation
I3
2.3 Implementation of the modules:
2.3.1 Effects of component tolerances
Load 2.3.2 Effects of other stages
2.3.3 Effects of the real character
operational amplifiers: gain-width
Band and "slew rate".
I3
2.4 Search and Troubleshooting
I5, I6, I8
|
Page 9 |
SPECIFIC CONTENT
Block / Theme /
Chapter
Paragraph
Indicators
Related
two
Block 3:
Development
digital part
3.1 Power of the digital part:
3.1.1 Reduced switching noise
3.1.2 Decoupling Capacitors
I4
3.2 Generation of clock signals
3.2.1 The timer NE555
3.2.2 Obtaining defined flanks
I4
3.3 Implementation of the modules
3.3.1 Intended Use of integrated circuits
CMOS
3.3.2 Precautions sequential circuits:
times "setup" and "hold".
3.3.3 Synchronization signals
3.3.4 Logical status display: LEDs and displays
I4
3.4 Searching and Troubleshooting
I5, I6, I8
Block 4:
Preparation of
documentation
technique
4.1 Drafting of technical documentation
I9
4.2 Overview of measurements and theoretical diagrams
(Bode and timelines)
I7
4.3 Explanation of the differences between the data
calculated and measured.
I9
Qualification Criteria
Students will be evaluated, by default, through ongoing evaluation. The
qualification of the subject will be as follows:
FINAL NOTE = 20% of the first oral evaluation MILESTONE + 60% Oral Assessment
final circuit + 20% Development of improvements.
Laboratory evaluation is performed by controlling knowledge oral
on practical design, functioning and adaptation to the specifications,
knowledge of the use of laboratory equipment and writing memory
written.
In compliance with the Regulatory Evaluation of the Technical University of
Madrid, students who wish to be evaluated by a single final exam
provided that they inform the Director of the Department of Engineering
Electronics on application in the register of the School
Telecommunication Engineering. This request can be made until the day
prior to the official announcement of the final exam. For eligible for
final exam mode, the score will be obtained as follows:
FINAL NOTE = 80% oral evaluation of the complete system (memory, knowledge
on the design and operation of the practice) + 20% Improvements. DATE:
Week 15 of the course. PLACE: Laboratory B-043
Analog Electronics (ELAN)
Digital Electronics (EDIG)
The main objective of this course is to obtain a basic level of Digital Electronics knowledge and set the stage to perform the analysis and design of complex digital electronic circuits. This training is subjects completed in subsequent courses such as: Circuits Electronics, Digital Systems I and II, Electronic Systems Engineering, Processor Architecture and Design of Digital Electronic Systems.
The most significant evolution of digital electronics in recent years has been on the degree of complexity of the systems that are carried with it, from simple components to complete systems performing. For address the problem of high complexity has chosen to make a approach that defines new levels of abstraction on the classic logic, such as RTL and functional.
In the approach of the program is part of the course with an introduction of electrical and logical levels to focus then the greater weight of thesubject to structural and functional levels, for introducing the VHDL hardware description language.
The main objective of this course is to obtain a basic level of Digital Electronics knowledge and set the stage to perform the analysis and design of complex digital electronic circuits. This training is subjects completed in subsequent courses such as: Circuits Electronics, Digital Systems I and II, Electronic Systems Engineering,
Processor Architecture and Design of Digital Electronic Systems.
The most significant evolution of digital electronics in recent years has been on the degree of complexity of the systems that are carried with it, from simple components to complete systems performing. For address the problem of high complexity has chosen to make a approach that defines new levels of abstraction on the classic logic, such as RTL and functional.
In the approach of the program is part of the course with an introduction of electrical and logical levels to focus then the greater weight of the subject to structural and functional levels, for introducing the VHDL hardware description language.
Learning Objectives
Powers assigned to the subject and level of
ACQUISITION
Code
Competition
Level
CG1-
CG13
All subjects contribute Curriculum
greater or lesser extent to the achievement of the
general skills of the graduate profile.
1
CECT9
Capacity for analysis and design of combinational circuits
and sequential, synchronous and asynchronous, and use of
microprocessors and integrated circuits.
3
CECT10
Knowledge and application of the fundamentals of languages
description of hardware devices
2
LEGEND:
Acquisition Level 1: Basic
Acquisition level 2: Middle
Acquisition Level 3: Advanced
SPECIFIC CONTENT
Block / Topic / Chapter
Paragraph
Indicators
Related
Topic 1: Coding
Information
1.1 Introduction Digital Electronics
I1
1.2 Abstraction digital (vs. analog. Digital)
I1
1.3 Numbering Systems
I1
1.4 Representation negative numbers
I1
1.5 Boolean algebra. Axioms
I2, I3
1.6 Basic Operators. Truth Table
I2, I3
1.7 Logic gates simple and complex
I2, I3
1.8 Karnaugh Maps
I2, I3
2.1 Introduction to programmable logic devices
to hardware description languages (VHDL)
I7
Item 2: Devices
2.2 Structure VHDL code
I7
Programmable Logic (VHDL)
2.3 Basic Syntax
I7
Item 3: Circuits
Combinational
3.1 Multiplexers.
I4, I7
3.2 Interconnection of several MUXes.
I4
3.3 Implementation of functions with MUXes.
I4
3.4 Encoders and Decoders
I4, I7
3.5 Interconnection of multiple coders
I4
3.6 Comparators
I4, I7
3.7 Adder
I4, I7
Nvm 08.03
I4
Item 4: Circuits
Sequential
4.1 Basic bistable element
I5
4.2 Set-Reset Scale.
I5
4.3 Bistable level assets (latch)
I5
4.4 Latch CLK edge assets (flip-flops): type-D,
JK and T-type
I5
4.5 Timing.
I5
4.6 Records Storage.
I5, I7
4.7 Counters
I5, I7
4.8 Shift registers
I5, I7
Item 5: Automata
5.1 Moore and Mealy machines.
I6
5.2 State Diagram.
I6, I7
5.3 Table of automata transitions.
I6
Qualification Criteria
Students will be assessed by continuous assessment default. In
compliance with the Regulations Assessment of the Technical University of Madrid,
Students who wish to be evaluated by a single long final test
when you inform the Director of the Department of Electronic Engineering
on application to the registry of the School of
Telecommunications Engineers before the day November 20, 2012. The
presentation of this paper constitute a waiver automatic continuous assessment.
The final mark will be obtained through continuous assessment sum of the
ratings for the following evaluation activities:
• Resolution and delivery of classroom exercises: mean 10% of the grade
end.
• 4-control tests conducted during class time representing
A total of 10% of the final grade.
• 2 partial evaluation tests: the first of which represents 30% of the
final grade and the second by 50%
Sistemas Digitales II
Sistemas Digitales I
4. Objetivos de Aprendizaje.
COMPETENCIAS ASIGNADAS A LA ASIGNATURA Y SU NIVEL DE ADQUISICIÓN
Código
Competencia
Nivel
CG1-CG5
Todas las asignaturas del Plan de Estudios contribuyen en mayor o menor medida a la consecución de las competencias generales del perfil de egreso.
-
CG6
Uso de la lengua inglesa.
1
CG9
Uso de Tecnologías de la Información y de las Comunicaciones.
2
CG12
Organización y planificación
1
CECT1
Capacidad para aprender de manera autónoma nuevos conocimientos y técnicas adecuados para la concepción, el desarrollo o la explotación de sistemas y servicios de telecomunicación.
1
CECT2
Capacidad de utilizar aplicaciones de comunicación e informáticas (ofimáticas, bases de datos, cálculo avanzado, gestión de proyectos, visualización, etc.) para apoyar el desarrollo y explotación de redes, servicios y aplicaciones de telecomunicación y electrónica.
2
CECT3
Capacidad para utilizar herramientas informáticas de búsqueda de recursos bibliográficos o de información relacionada con las telecomunicaciones y la electrónica.
1
CECT6
Capacidad de concebir, desplegar, organizar y gestionar redes, sistemas, servicios e infraestructuras de telecomunicación en contextos residenciales (hogar, ciudad y comunidades digitales), empresariales o institucionales responsabilizándose de su puesta en marcha y mejora continua, así como conocer su impacto económico y social
1
CECT9
Capacidad de análisis y diseño de circuitos combinacionales y secuenciales, síncronos y asíncronos, y de utilización de microprocesadores y circuitos integrados.
2
CECT11
Capacidad de utilizar distintas fuentes de energía y en especial la solar fotovoltaica y térmica, así como los fundamentos de la electrotecnia y de la electrónica de potencia.
1
LEYENDA: Nivel de adquisición 1: Básico Nivel de adquisición 2: Medio Nivel de adquisición 3: Avanzado
5. Sistema de evaluación de la asignatura
INDICADORES DE LOGRO
Ref
Indicador
Relaciona-do con RA
I1
Conocer los elementos básicos de un sistema microcontrolador (el microcontrolador interno, los registros y buses, las unidades funcionales, y las unidades para el cálculo de direcciones), su arquitectura y estructura funcional y el proceso de ejecución de instrucciones. Identificar características y aplicaciones de las distintas gamas y tipos procesadores y memorias.
RA1 RA2 RA3
I2
Análisis y programación en lenguaje ensamblador, incluyendo conocimiento detallado de las directivas del ensamblador, el modelo de programación y el juego de instrucciones de un microprocesador.
RA2 RA3 RA5
I3
Conocer la organización de datos en memoria, los modos de direccionamiento y el funcionamiento de la pila en un sistema microprocesador.
RA2
Nanotecnología para la Información y las Comunicaciones (NTIC)
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